CS5541

18

DS500PP1

erroneous. The OD flag bit will be cleared to logic 0

when the modulator becomes stable.

The Overrange Flag (OF) bit is set to a logic 1 any

time the input signal is: 1) more positive than posi-

tive full scale, 2) more negative than zero (unipolar

mode), 3) more negative than negative full scale

(bipolar mode). It is cleared back to logic 0 when-

ever a conversion word occurs which is not over-

ranged.

The last 24 SCLKs are used to clock data out of the

conversion data register.

Table 2 and Table 3 illustrate the output coding for

the CS5541. Unipolar conversions are output in bi-

nary format and bipolar conversions are output in

two’s complement format.

2.9.9 Digital Filter

The CS5541 includes two digital filters. The first

filter which achieves simultaneous rejection of

50/60 Hz provides single conversion settling at

13.4 SPS throughput or four conversion settling at

53.7 SPS throughput. The second filter which

achieves 16-bit performance provides single con-

version settling at 64.8 SPS throughput or four con-

version settling at 260 SPS throughput.

The first filter (13.4 SPS and 53.7 SPS throughput)

is optimized to yield better than 80 dB rejection be-

tween 47 Hz to 63 Hz (i.e. 80 dB minimum rejec-

tion for both 50 Hz and 60 Hz) when the master

clock is 32.768 kHz. The filter has a response as

shown in Figure 14.

The second filter is optimized for higher through-

put, and does not provide 50 Hz or 60 Hz rejection.

It has a frequency response that is shown in Figure

15.

To ease code development, each filter (13.4 SPS or

64.8 SPS throughput) has a mode that only outputs

tion).

D31

D30

D29

D28

D27

D26

D25

D24

01

1

1

1

CH

OD

OF

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

MSB

22212019

18

17

16

15

14

13

12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

11

10

98

76

5

4

3

2

1

LSB

Table 2. Output Conversion Data Register Description (24 bits + flags)

Note:

VFS in the table equals the voltage between ground and full scale for the unipolar mode, or the voltage

between

± full scale for the bipolar mode. See text about error flags under overrange conditions.

Unipolar Input Voltage

Offset Binary

Bipolar Input Voltage

Two’s

Complement

>(VFS-1.5 LSB)

FFFFFF

>(VFS-1.5 LSB)

7FFFFF

VFS-1.5 LSB

FFFFFF

-----

FFFFFE

VFS-1.5 LSB

7FFFFF

-----

7FFFFE

VFS/2-0.5 LSB

800000

-----

7FFFFF

-0.5 LSB

000000

-----

FFFFFF

+0.5 LSB

000001

-----

000000

-VFS+0.5 LSB

800001

-----

800000

<(+0.5 LSB)

000000

<(-VFS+0.5 LSB)

800000

Table 3. CS5541 24-Bit Output Coding