AX68004LF datasheet(51/57 Pages) ASIX

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AX6800x

2/4-Port USB KVM Switch SoC

4.5.6 PS/2 Interface Timing

4.5.6.1 PS2 Host Receiving Data Timing

Symbol

Description

Min

Typ

Max

Units

TSU_S

Time from Data transition to falling edge of CLK

TOD

Time from rising edge of CLK to Data transition

TCH-5

TCL

Duration of CLK low (inactive)

TCH

Duration of CLK high (active)

TSU_S

Time from Data transition to falling edge of CLK

Figure 4-8: PS2 Host Receiving Data Timing Diagram and Table

4.5.6.2 Host Sending Data Timing

Symbol

Description

Min

Typ

Max

Units

TINH

Host bring CLK low to inhibit I/O (request to send)

(TINH

8 -

1) * 10

TCL

Duration of CLK low (inactive)

TCH

Duration of CLK high (active)

THLD

Time from low to high CLK transition when Device

samples Data

TSU_A

Time from falling edge of Data to falling edge of CLK

TDT

Time from rising edge of CLK11 to rising edge of Ack Bit -

8: The TINH is the Inhibit timing register.

Figure 4-9: PS2 Host Sending Data Timing Diagram and Table

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