FXPS7115D4 datasheet(44/72 Pages) NXP

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NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

FXPS7115D4

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Product data sheet

Rev. 3 — 5 December 2019

44 / 72

7.7.13 INT_CFG - interrupt configuration register (address 45h)

The interrupt configuration register contains configuration information for the interrupt

output. This register can be written during initialization but is locked once the ENDINIT bit

is set (see Section 7.7.4 "DEVLOCK_WR - lock register writes register (address 10h)").

The register is included in the read/write array error detection.

Table 70. INT_CFG - interrupt configuration register (address 45h) bit allocation

Bit

Symbol

reserved

INT_PS[1:0]

INT_POLARITY

reserved

Reset

Access

R/W

Table 71. INT_CFG - interrupt configuration register (address 45h) bit description

Bit

Symbol

Description

5 to 4

INT_PS[1:0]

The INT_PS[1:0] bits set the programmable pulse stretch time for the interrupt output. Pulse stretch times are derived

from the internal oscillator, so the tolerance on this oscillator applies.

00 — 0 ms

01 —16.000 ms to 16.512 ms

10 — 64.000 ms to 64.512 ms

11 — 256.000 ms to 256.512 ms

If the pulse stretch function is programmed to '00', the interrupt pin is asserted if and only if the interrupt condition exists

after the most recent evaluated sample. The interrupt pin is deasserted if and only if an interrupt condition does not

exist after the most recent evaluated sample.

If the pulse stretch function is programmed to a non-zero value, the interrupt pin is controlled only by the value of the

pulse stretch timer value. If the pulse stretch timer value is non-zero, the interrupt pin is asserted. If the pulse stretch

timer is zero, the interrupt pin is deasserted. The pulse stretch counter continuously decrements until it reaches zero.

The pulse stretch counter is reset to the programmed pulse stretch value if and only if an interrupt condition exists after

the most recent evaluated sample.

INT_POLARITY

The interrupt polarity bit controls whether the interrupt is activated for values within or outside of the window selected

by the high and low threshold registers. With this bit and the programmable thresholds, a window comparator can be

programmed for activation either within or outside of a window.

0 — Interrupt activated, if the value is outside the window

1 — Interrupt activated, if the value is inside the window

7.7.14 P_INT_HI, P_INT_LO - interrupt window comparator threshold registers

(address 46h to 49h)

The interrupt threshold registers contain the high and low window comparator thresholds

for pressure to be used to activate and deactivate the interrupt output. These registers

can be written during initialization but are locked once the ENDINIT bit is set (see

Section 7.7.4 "DEVLOCK_WR - lock register writes register (address 10h)"). The register

is included in the read/write array error detection.

Table 72. P_INT_HI, P_INT_LO - interrupt window comparator threshold registers (address 46h to 49h) bit allocation

Location

Bit

Address

46h

PIN_INT_HI_L

PIN_INT_HI[7:0]

47h

PIN_INT_HI_H

PIN_INT_HI[15:8]

48h

PIN_INT_LO_L

PIN_INT_LO[7:0]

49h

PIN_INT_LO_H

PIN_INT_LO[15:8]

Reset

Access

R/W

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