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SSD1818 Series
Rev 1.2
08/2002
SOLOMON
3
BLOCK DIAGRAM
Figure 1 - Block Diagram
ICONS
ROW0 ~
ROW63
SEG0 ~SEG103
HV Buffer Cell Level Shifter
Display Data Latch
GDDRAM
104 X 65 Bits
Display
Timing
Generator
Oscillator
Level
Selector
LCD Driving
Voltage
Generator
2X/ 3X/ 4X/ 5X
DC/ DC Converter,
Voltage Regulator,
Contrast Control,
Bias Divider with
integrated
capacitors,
Temperature
Compensation
Command Decoder
Parallel / Serial
Interface
Command Interface
MSTAT
M
DOF
M/S
CL
CLS
VSS
VDD
C0
C1
V
L6
V
L5
VL4
VL3
VL2
VDD
/RES
P/S
/CS1 CS2
D/C
(RD)
E
(WR)
R/W
C68/80
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
[SCK]
[SDA]
VEE
VSS1
C4N
C3N
C1P
C1N
C2N
C2P
IRS