K4H560438E-ZC datasheet(8/23 Pages) SAMSUNG

8 / 23 page

DDR SDRAM

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free

Rev. 1.1 October, 2004

Command Truth Table

(V=Valid, X=Don

′t Care, H=Logic High, L=Logic Low)

COMMAND

CKEn-1 CKEn

RAS

CAS

BA0,1 A10/AP

A0 ~ A9,

A11,A12

Note

Extended MRS

OP CODE

1, 2

Mode Register Set

OP CODE

1, 2

Refresh

Auto Refresh

Self

Refresh

Entry

Exit

Bank Active & Row Addr.

Row Address

Read &

Column Address

Auto Precharge Disable

Column

Address

Auto Precharge Enable

Write &

Column Address

Auto Precharge Disable

Column

Address

Auto Precharge Enable

4, 6

Burst Stop

Precharge

Bank Selection

All Banks

Active Power Down

Entry

Exit

Precharge Power Down Mode

Entry

Exit

DM(UDM/LDM for x16 only)

No operation (NOP) : Not defined

1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)

2. EMRS/MRS can be issued only at all banks precharge state.

A new command can be issued 2 clock cycles after EMRS or MRS.

3. Auto refresh functions are same as the CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.

If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.

6. During burst write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

7. Burst stop command is valid at every burst length.

8. DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).

DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges

(Write DM latency is 0).

9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.

Note :

K4H560438E-ZC Arkusz danych(PDF) 8 Page - Samsung semiconductor

K4H560438E-ZC Arkusz danych(HTML) 8 Page - Samsung semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Arkusz danych Pobierz

Link URL