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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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STM8S Arkusz danych(PDF) 99 Page - STMicroelectronics |
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STM8S Arkusz danych(HTML) 99 Page - STMicroelectronics |
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99 / 467 page  DocID14587 Rev 14 99/467 RM0016 Clock control (CLK) 104 9.9.11 HSI clock calibration trimming register (CLK_HSITRIMR) Address offset: 0x0C Reset value: 0x00 9.9.12 SWIM clock control register (CLK_SWIMCCR) Address offset: 0x0D Reset value: 0bXXXX XXX0 7 654 3210 Reserved HSITRIM[3:0] rrw rw rw rw Bits 7:4 Reserved, must be kept cleared. Bits 3:0 HSITRIM[3:0] HSI trimming value These bits are written by software to fine tune the HSI calibration. Note: In high density STM8S and STM8AF devices, only bits 2:0 are available. In other devices, bits 3:0 are available to achieve a better HSI resolution. Compatibility with bits 2:0 can be selected through options bytes (refer to datasheet). 7 654 3210 Reserved SWIMCLK r rw Bits 7:1 Reserved. Bit 0 SWIMCLK SWIM clock divider This bit is set and cleared by software. 0: SWIM clock divided by 2 1: SWIM clock not divided by 2 |
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