137

80C286/883

NOTES:

1. PCLK indicates which processor cycle phase will occur on the

next CLK. PCLK may not indicate the correct phase until the first

cycle is performed.

2. These inputs are asynchronous. The setup and hold times shown

assure recognition for testing purposes.

FIGURE 3. 80C286/883 ASYNCHRONOUS INPUT SIGNAL

TIMING

NOTE:

1. When RESET meets the setup time shown, the next CLK will

start or repeat

φ1 of a processor cycle.

FIGURE 4. 80C286/883 RESET INPUT TIMING AND SUBSE-

QUENT PROCESSOR CYCLE PHASE

φ2

BUS CYCLE TYPE

CLK

φ1

PCLK

(SEE NOTE 1)

INTR, NMI

HOLD, PEREQ

(SEE NOTE 2)

ERROR, BUSY

(SEE NOTE 2)

19

19

4

5

5

4

φ2

7

RESET

φ1

φ1

φ2

6

CLK

(SEE NOTE 1)

CLK

RESET

φ2

φ2

φ1

7

6

(SEE NOTE 1)