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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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ADC3541 Arkusz danych(PDF) 33 Page - Texas Instruments |
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ADC3541 Arkusz danych(HTML) 33 Page - Texas Instruments |
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33 / 68 page  D15..0 DCLK DCLK SDR Sample A0 Sample A1 D15 (MSB) D14 D2 D1 D0 D12..5 DCLK DCLK DDR CMOS D12 D11 D7 D6 D5 Sample A0 Sample A1 D7 D6 D2 D1 D0 D15 D14 D10 D9 D8 D7 D6 D2 D1 D0 D15 D14 D10 D9 D8 Figure 7-33. Output Data Format in Real Decimation Table 7-4 illustrates the output interface data rate along with the corresponding DCLK frequency based on real decimation setting (M). Furthermore the table shows an actual lane rate example with complex decimation by 4. Table 7-5. Parallel CMOS Data Rate Examples with Decimation REAL/COMPLEX DECIMATION DECIMATION SETTING ADC SAMPLING RATE SDR/DDR CMOS DCLK DOUT Real M FS SDR FS / M FS / M DDR FS x 2 / M 4 65 MHz SDR 16.25 MHz 16.25 MHz DDR 32.5 MHz www.ti.com ADC3541 SBAS840 – JULY 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: ADC3541 |
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