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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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LIS25BATR Arkusz danych(PDF) 20 Page - STMicroelectronics |
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LIS25BATR Arkusz danych(HTML) 20 Page - STMicroelectronics |
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20 / 32 page  TDM interface specifications LIS25BA 20/32 DocID031510 Rev 4 4.6 TDM clocks and MCLK requirements The relationship between TDM clocks and MCLK should be: Both BCLK and WCLK must be obtained from MCLK by integer division. This requirement is mandatory since ADC is clocked by MCLK, so the TDM data rate must be perfectly synchronous in frequency and phase with the decimated ADC data rate. The BCLK/WCLK ratio must be an integer value. 4.7 I²C axis disable In TDM mode, a host processor can power down each axis of the LIS25BA accelerometer independently, overriding the I²C registers (AXISX_EN, AXISY_EN, AXISZ_EN in AXES_CTRL_REG (2Fh)) interface to reduce power consumption during operation. When an axis is powered down, the corresponding TDM slot will be put in HiZ. |
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