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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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AS80SSTVF16859 Arkusz danych(PDF) 8 Page - Alliance Semiconductor Corporation |
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AS80SSTVF16859 Arkusz danych(HTML) 8 Page - Alliance Semiconductor Corporation |
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8 / 13 page  AS80SSTVF16859 8/6/03, v.0.10 Alliance Semiconductor P. 8 of 13 Timing Requirements (Over recommended operating free-air temperature range, unless otherwise noted.) Guaranteed by design. Not 100% tested in production * This parameter is not necessarily production tested.. Switching Characteristics - DDRI / DDR333 (PC1600, PC2100, PC2700) (Over recommended operating free-air temperature range unless otherwise noted.) Switching Characteristics - DDRI-400 (PC3200) (Over recommended operating free-air temperature range unless otherwise noted.) Symbol Parameters VDDQ = 2.5V±0.2V VDDQ = 2.6V±0.1V Units Min Max Min Max fCLOCK Clock frequency 200 270 MHz tW Pulse duration, CK, CKLB high or low 2.5 2.5 ns tACT* Differential inputs active time1 1 Data inputs must be low a minimum time of tACT max, after RESETB is taken high 22 22 ns tINACT* Differential inputs inactive time2 2 Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max, after RESETB is taken low 22 22 ns tS Setup time, fast slew rate3,5 3 For data signal input slew rate > 1 V/ns Data before CLK ↑, CLKB ↓ 0.75 0.4 ns ns Setup time, slow slew rate4,5 4 For data signal input slew rte > 0.5 V/ns and < 1 V/ns 0.9 0.6 th Hold time, fast slew rate3,5 5 CLK, CLKB signals iput slew rates are > 1 V/ns Data after CLK ↑, CLKB ↓ 0.75 0.4 ns ns Hold time, slow slew rate4,5 0.9 0.6 Symbol From (input) To (output) VDD = 2.5 V ± 0.2 V Units Min Typ Max fmax 200 – – MHz tPD CLK, CLKB (TSSOP) Q 1.1 2.8 ns CLK, CLKB (VFQFN[MLF2]) Q 1.1 2.8 ns tphl RESETB Q – – 5.0 ns Symbol From (input) To (output) VDD = 2.6 V ± 0.1 V Units Min Typ Max fmax 210 MHz tPD CLK, CLKB (VFQFN[MLF2]) Simultaneous switching Q1.1 2.2 ns tPDSS Q 2.48 ns tphl RESETB Q 3.5 ns |
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