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ASM2P20805A Arkusz danych(PDF) 6 Page - Alliance Semiconductor Corporation |
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ASM2P20805A Arkusz danych(HTML) 6 Page - Alliance Semiconductor Corporation |
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6 / 11 page ![]() June 2005 ASM2P20805A rev 0.2 2.5V CMOS Dual 1-To-5 Clock Driver 6 of 11 Notice: The information in this document is subject to change without notice. Test Circuits and Waveforms Switch Position Test Conditions Symbol VCC = 2.5V ±0.2V Unit CL 15 pF RT ZOUT of pulse generator Ω RL 33 Ω tR / tF 1 (0V to 2.5V or 2.5V to 0V) nS Definitions: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. tR / tF = Rise/Fall time of the input stimulus from the Pulse Generator. Test Switch Disable Low Enable Low 4.6V Disable High Enable High GND |
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