August 2004

ASM4SSTVF16859

rev 2.0

Alliance Semiconductor

2575, Augustine Drive  Santa Clara, CA  Tel: 408.855.4900  Fax: 408.855.4999  www.alsc.com

Notice: The information in this document is subject to change without notice.

DDR 13-Bit to 26-Bit Registered Buffer

Features



Differential clock signals.



Meets SSTL_2 class II specifications on

outputs.





Available in 64-pin TSSOP, 64-pin TVSOP,

and 56-pin VFQFN packages.

Product Description

The ASM4SSTVF16859 is a universal 13/26 bit

register

(D F/F based), designed for 2.3V to 2.7V

levels, and is fully compliant with the JEDEC JC40,

JC42.5 DDR I specifications covering PC1600, PC

2100, PC2700, and PC3200 operational ranges ( DDR

400

– 200 MHz ). 13/26 bits refers to 2Q outputs for

each D input - designed for use in Stacked Registered

(stacked

Memory

Devices),

Buffered

DIMM

applications.

Data flow from D to Q is controlled by the differential

clock (CLK/CLKB) and a control signal (RESETB).

The positive edge of CLK is used to trigger the data

transfer, and CLKB is used to maintain sufficient noise

margins, whereas RESETB input is designed and

intended for use at power-up.

The ASM4SSTVF16859 supports a low power standby

mode of operation. A logic level low at RESETB,

assures that all internal registers and outputs (Q) are

reset to a logic low state, and that all input receivers,

data (D) buffers, and clock (CLK/CLKB) are switched

off. Note that RESETB should be supported with a

LVCMOS level at a valid state since VREF may not be

stable during power-up.

To ensure that outputs are at a defined logic state before a

stable clock has been supplied, RESETB must be held at a

logic low level during power-up.

In the JEDEC defined Registered DDR DIMM application,

RESETB is specified to be asynchronous with respect to

CLK/CLKB; therefore, no timing relationship can be

guaranteed between the two signals. When entering a

low-power standby state, the register will be cleared and

the outputs will be driven to a logic low level quickly

relative to the time to disable the differential input

receivers. This ensures there are no “glitches” on any

output. However, when coming out of low power standby

mode, the register will become active quickly relative to the

time taken to enable the differential input receivers. When

the data inputs are at a logic level low and the clock is

stable during the low-to-high transition of RESETB until the

input receivers are fully enabled, the design ensures that

the outputs will remain at a logic low level.

Applications

•

JEDEC and Non-JEDEC DDR Memory Modules

•

Stacked or Planar configurations.

•

Supports PC1600 - PC2100 - PC2700 - PC3200

•

DDR 400 compliant (200MHz+).

•

SSTL_2 I/O.

•

Provides a complete support solution for JEDEC

JC42.5 DIMMs’ when used with the ASM5CVF857

Zero Delay Buffer.