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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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BQ27Z561-R2 Arkusz danych(PDF) 7 Page - Texas Instruments |
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BQ27Z561-R2 Arkusz danych(HTML) 7 Page - Texas Instruments |
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7 / 22 page  7.13 Voltage Reference1 (REF1) Unless otherwise noted, characteristics noted under conditions of TA = –40℃ to 85℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VREF1 Internal reference voltage(1) 1.195 1.21 1.227 V VREF1_DRIFT Internal reference voltage drift TA = –40 °C to 85°C –80 +80 PPM/C (1) Used for CC and LDO 7.14 Voltage Reference2 (REF2) Unless otherwise noted, characteristics noted under conditions of TA = –40℃ to 85℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VREF2 Internal reference voltage(1) 1.2 1.21 1.22 V VREF2_DRIFT Internal reference voltage drift TA = –40 °C to 85°C –20 20 PPM/°C (1) Used for ADC 7.15 Flash Memory Unless otherwise noted, characteristics noted under conditions of TA = –40℃ to 85℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Data retention 10 100 Years Flash programming write cycles Data Flash 20000 Cycles Instruction Flash 1000 Cycles t(ROWPROG) Row programming time 40 µs t(MASSERASE) Mass-erase time TA = –40°C to 85°C 40 ms t(PAGEERASE) Page-erase time TA = –40°C to 85°C 40 ms IFLASHREAD Flash read current TA = –40°C to 85°C 1 mA IFLASHWRTIE Flash write current TA = –40°C to 85°C 5 mA IFLASHERASE Flash erase current TA = –40°C to 85°C 15 mA 7.16 I2C I/O Unless otherwise noted, characteristics noted under conditions of TA = –40℃ to 85℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High-level input voltage SCL, SDA/HDQ, VREG18 = 1.8 V 1.26 V VIL Low-level input voltage low VREG18 = 1.8 V 0.54 V VOL Low-level output voltage IOL = 1 mA, VREG18 = 1.8 V 0.36 V CI Input capacitance 10 pF Ilkg Input leakage current 1 µA 7.17 I2C Timing — 100 kHz PARAMETER TEST CONDITIONS MIN NOM MAX UNIT fSCL Clock operating frequency SCL duty cycle = 50% 100 kHz tHD:STA Start condition hold time 4.0 µs tLOW Low period of the SCL Clock 4.7 µs tHIGH High period of the SCL Clock 4.0 µs tSU:STA Setup repeated START 4.7 µs tHD:DAT Data hold time (SDA input) 0 ns tSU:DAT Data setup time (SDA input) 250 ns tr Clock rise time 10% to 90% 1000 ns www.ti.com BQ27Z561-R2 SLUSE22 – SEPTEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: BQ27Z561-R2 |
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