IIS2MDC datasheet(32/40 Pages) STMICROELECTRONICS

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IIS2MDC

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8.7

CFG_REG_C (62h)

Table 30. CFG_REG_C register

Table 31. CFG_REG_C register description

8.8

INT_CTRL_REG (63h)

The interrupt control register is used to enable and to configure the interrupt recognition.

Table 32. INT_CRTL_REG register

INT_on_PIN

I2C_DIS

BDU

BLE

0(1)

1. This bit must be set to ‘0’ for the correct operation of the device.

Self_test

DRDY_on_PIN

INT_on_PIN

If '1', the INTERRUPT signal (INT bit in INT_SOURCE_REG (64h)) is driven

on the INT/DRDY pin. The INT/DRDY pin is configured in push-pull output mode.

Default value: 0

I2C_DIS

If ‘1’, the I2C interface is inhibited. Only the SPI interface can be used.

BDU

If enabled, reading of incorrect data is avoided when the user reads asynchro-

nously. In fact if the read request arrives during an update of the output data, a

latch is possible, reading incoherent high and low parts of the same register. Only

one part is updated and the other one remains old.

BLE

If ‘1’, an inversion of the low and high parts of the data occurs.

Self_test

If ‘1’, the self-test is enabled.

DRDY_on_PIN

If '1', the data-ready signal (Zyxda bit in STATUS_REG (67h)) is driven on the

INT/DRDY pin. The INT/DRDY pin is configured in push-pull output mode.

Default value: 0

XIEN

YIEN

ZIEN

0(1)

1. This bit must be set to ‘0’ for the correct operation of the device.

0(1)

IEA

IEL

IEN

Table 33. INT_CTRL_REG register description

XIEN

Enables the interrupt detection for the X-axis. Default: 1

(1: enabled; 0: disabled)

YIEN

Enables the interrupt detection for the Y-axis. Default: 1

(1: enabled; 0: disabled)

ZIEN

Enables the interrupt detection for the Z-axis. Default: 1

(1: enabled; 0: disabled)

IEA

Controls the polarity of the INT bit (INT_SOURCE_REG (64h)) when an interrupt

occurs. Default: 0

If IEA = 0, then INT = 0 signals an interrupt.

If IEA = 1, then INT = 1 signals an interrupt.

IEL

Controls whether the INT bit (INT_SOURCE_REG (64h)) is latched or pulsed. Default: 0

If IEL = 0, then INT is pulsed.

If IEL = 1, then INT is latched.

Once latched, INT remains in the same state until INT_SOURCE_REG (64h) is read.

IEN

Interrupt enable. When set, enables the interrupt generation. The INT bit

is in INT_SOURCE_REG (64h). Default: 0

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