MAS 3504D

Micronas

11

A schematic timing diagram of the SDO interface in 16 bit/sample mode with delayed data by 1 clock cycle is shown

in Fig. 2–5.

Fig. 2–5: Schematic timing of the SDO interface in 16bit/sample mode

2.6.5.2. Example 2:32 Bit/Sample (Inverted SOI)

If the serial output generates 32 bits per audio sample, only the first 20 bits will carry valid audio data. The 12 trailing

bits are set to zero by default (see Fig. 2–6).

Fig. 2–6: Schematic timing of the SDO interface in 32 bit/sample mode

SOC

SOD

SOI

left 16-bit audio sample

right 16-bit audio sample

15 14 13 12 11 10 9

8

7

65432

10

13 12 11 10 9 8

7

6 5 4

32

10

15 14

30 29 28 27 26 25

31 30 29 28 27 26 25

7654

3210

left 32-bit audio sample

right 32-bit audio sample

SOC

SOD

SOI

...

...

31

...