*direct on pins

TLE5041plusC

Functional Description

2.4.2

Calibrated Mode

In calibrated mode the output will switch at zero-crossing of the input signal. Oscillations of the Offset DAC are

avoided by switching into a low-jitter mode. Signals below a defined threshold d

Β

interface to avoid unwanted output switching. Offset determination is done continuously in calibrated mode.

The phase shift between input and output signal is no longer determined by the ratio between digital noise constant

and signal amplitude. Therefore a sudden change in the phase shift may occur during the transition from

uncalibrated to calibrated mode.

2.4.3

lower than 1 Hz. Depending on their amplitude edges slower than

Δt

constant (dB

needs to be exceeded before

Δt

2.4.4

Undervoltage behavior

The voltage supply comparator has an integrated hysteresis V

< 4.5V. This determines the minimum required supply voltage VDD of the chip. A minimum hysteresis V

is implemented thus avoiding a toggling of the output when the supply voltage VDD is modulated due to the

R

Figure 7

Undervoltage behavior

Data Sheet

12

V 1.2, 2018-01-18