6.1.3

Minimizing write delays by polling on ACK

During the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its

9 DC and AC parameters, but the typical time is shorter. To make use of this, a polling sequence can be used by

the bus master.

The sequence, as shown in Figure 7, is:

•

Initial condition: a write cycle is in progress.

•

Step 1: the bus master issues a start condition followed by a device select code (the first byte of the new

instruction).

•

Step 2: if the device is busy with the internal write cycle, no ACK will be returned and the bus master goes

back to step 1. If the device has terminated the internal write cycle, it responds with an ACK, indicating that

the device is ready to receive the second part of the instruction (the first byte of this instruction having been

sent during step 1).

Note:

In case of write to chip enable register when C2, C1 and C0 are re-configured, the device will return ACK only if:

- chip enable address of the device select code is equal to the new C2, C1 and C0 values

- an internal write cycle is completed (new C2, C1 and C0 values have been programmed in the chip enable

register).

Write cycle

in progress

Next

operation is

addressing the

memory

Start condition

ACK

returned

YES

NO

YES

NO

Re-start

Stop

Data for the

write operation

Send address

and receive ACK

YES

NO

Continue the

write operation

Continue the

random read operation

Device select

with RW = 1

First byte of instruction

with RW = 0 already

decoded by the device

Device select

with RW = 0

StartCondition

1.

The seven most significant bits of the device select code of a random read (bottom right box in the figure)

must be identical to the seven most significant bits of the device select code of the write (polling instruction

in the figure).

M24128X-FCU

Write operations on memory array

DS12680 - Rev 2

page 12/35