TPS2340A

SLUS528A – MARCH 2002 – REVISED AUGUST 2002

21

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APPLICATION INFORMATION

package information

The TPS2340A dissipates very little heat under normal operating conditions. However, when the TPS2340A

is used with a load that exceeds PCI specifications either due to a fault or a specification violation, power

dissipation increases as the square of load current. To allow reliable operation with high power dissipation, the

TPS2340A is packaged in a PowerPAD

t molded quad flat pack with heat-conducting tab on the underside. This

package offers thermal resistance from junction to case of approximately 8

°C/W. In a typical layout, thermal

resistance from junction to ambient is approximately 35

°C/W.

For optimum heat conduction and system reliability, the heat-conducting tab should be soldered directly to a

10-mm square copper area on the circuit board tied to M12VIN voltage potential. To increase heat conduction,

add plated vias to the copper area directly under the part and connect these vias to copper planes around 100%

of their perimeter. These vias conduct heat away from the top layer of the circuit board and into other layers and

should not use thermal reliefs (also known as thermals or webs). To prevent solder wicking into the vias, the

vias should either be drilled to a size small enough to allow complete filling of the vias during hole plating or

should be covered by solder mask on the back of the circuit board.

The TPS2340A TQFP–80 package conforms to JEDEC MS–026. For more information on the PowerPAD

package, consult TI PowerPAD Technical Brief (SLMA002).

device testability

Table 11. Test Mode Configuration

PGOOD

TEST

SODO/MODE1

SIDO/MODE0

OPERATING MODE

↑

0

MODE1

MODE0

Normal operation mode, latch MODE inputs

1

0

SODO

SIDO

Normal operation mode, drive SODO and SIDO

↑

1

0

0

NAND tree test mode

↑

1

0

1

Tri–state test mode (all pins tri-stated)

↑

1

1

X

Reserved

1

1

SODO

SIDO

Normal operation, but Pwrenx driven on PWRLEDx, Faultx

driven on ATTLEDx.

NOTE:

X = Don’t care, x = slot A or B; shaded cells signify test modes.

When TEST is asserted after PGOOD is asserted, the device enters a run-time test mode. When this test mode

is enabled, the slot-specific PWRLEDx output asserts when the slot’s internal Pwrenx signal is asserted.

Similarly, the ATTLEDx output asserts when the corresponding ANDed slot Faultx signal is asserted.