MITSUBISHI < STD. LINEAR ICs >

M62320P,FP

2/20,1998(rev) (

/ 9 )

MITSUBISHI ELECTRIC

8-BIT I/O EXPANDER for I C BUS

2

• In case the I/O setting is different between each terminals.

An example : the parallel port terminals of D0 to D3 and D4 to D7 are assigned as output and input terminals,

respectively.

The input data is taken into the input latch on every 8th negative-going edge of the SCL clock through the

terminal assigned as an input, and then the latched data is output via the SDA line.

The data of the output assigned terminal is also handled in the same procedures as above.

D0 to D3

SCL

SDA

0

1

1

1 A2 A1 A0 0

A

1

234

5

6

7

8

1

234

5

6

7

8

DATA

DATA

Hi-Z

D4 to D7

Hi-Z

start condition

slave address

I / O setting

stop condition

Data output

Data output

• Write mode

The terminal assigned as an output provides the data written in the output data latch.

After power-on, all terminals are reset to the input-state. Then an initial data low of the output latch are

output after the I/O setting has been done. Finally the assigned output are provided after the 8-bit data

transmission.

The terminal assigned as an input keeps the input condition (high-impedance) regardless of 8-bit data

setting.

SCL

SDA

01

1

1 A2 A1 A0 1

A

12

3

456

78

1

2

34

567

8

DATA

DATA

DATA

D4 to D7

output

Hi-Z

D0 to D3

D4 to D7

(instance)

start condition

slave address

stop condition

data latch

data latch

data latch

• Read mode

8