LM1012T datasheet(2/6 Pages) LEIDITECH

2 / 6 page

SPECIFICATIONS (TA = 25_C UNLESS OTHERWISE NOTED)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Static

Gate Threshold Voltage

VGS(th)

VDS = VGS, ID = 250 mA

0.45

0.9

Gate-Body Leakage

IGSS

VDS = 0 V, VGS = "4.5 V

"0.5

"1.0

Zero Gate Voltage Drain Current

IDSS

VDS = 20 V, VGS = 0 V

0.3

100

Zero Gate Voltage Drain Current

IDSS

VDS = 20 V, VGS = 0 V, TJ = 85_C

On-State Drain Currenta

ID(on)

VDS = 5 V, VGS = 4.5 V

700

VGS = 4.5 V, ID = 600 mA

0.41

0.70

Drain-Source On-State Resistancea

rDS(on)

VGS = 2.5 V, ID = 500 m A

0.53

0.85

DS(on)

VGS = 1.8 V, ID = 350 m A

0.70

1.25

Forward Transconductancea

gfs

VDS = 10 V, ID = 400 mA

1.0

Diode Forward Voltagea

VSD

IS = 150 mA, VGS = 0 V

0.8

1.2

Dynamicb

Total Gate Charge

750

Gate-Source Charge

Qgs

VDS = 10 V, VGS = 4.5 V, ID = 250 mA

Gate-Drain Charge

Qgd

225

Turn-On Delay Time

td(on)

Rise Time

VDD = 10 V, RL = 47 W

Turn-Off Delay Time

td(off)

VDD = 10 V, RL = 47 W

ID ^ 200 mA, VGEN = 4.5 V, RG = 10 W

Fall Time

Notes

Pulse test; pulse width v 300 ms, duty cycle v 2%.

Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation

of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

LM1012T

Rev :

www.leiditech.com

01.06.2018

2/6

LM1012T Arkusz danych(PDF) 2 Page - Shanghai Leiditech Electronic Technology Co., Ltd

LM1012T Arkusz danych(HTML) 2 Page - Shanghai Leiditech Electronic Technology Co., Ltd

Html Pages

1 2 3 4 5 6

Arkusz danych Pobierz

Link URL