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STV7618 Arkusz danych(PDF) 15 Page - STMicroelectronics |
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STV7618 Arkusz danych(HTML) 15 Page - STMicroelectronics |
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15 / 16 page ![]() STV7618 15/15 Figure 2. Test configuration 8 - TESTED WAFER DISCLAIMER All wafers are tested and guaranteed to comply with all datasheet limits up to the point of wafer sawing for a period of ninety (90) days from the delivery date. We remind you that it is the customer’s responsibility to test and qualify their application in which the die is used. ST Microelectronics is ready to support the customer when qualifying the product. VDOUTH IDOUTH VSSP V DOUTL I DOUTL VSSP VPP=VSSP VPP=VSSP Output sinking current as positive value, sourcing current as negative value |
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