AX88850

PRELIMINARY

ASIX ELECTRONICS CORPORATION

32

4.12 Port Management Counter Registers

Each of the 18 ports of the AX88850 has a set of 4 event counters whose values can be read or pre-set (written)

through the Port Management Counter Registers. When PCS (symbol) mode is selected, there is a set of false carrier

counter / per port build-in on the chip. As for MII mode , the false carrier counter will be available on PHY, note that

some PHY chip manufacturer not support those functions.

4.12.1 Short Event Counter Registers

Per port (“n” =port number) counters that indicate the number of Carrier Events that were active for less than the

ShortEventMaxTime, which is defined as between 74 and 82 (76 nominal) bit times.

Bit

Bit Name

Access

Bit Description

D15-D0

P“n”_SE[15:0]

R/W

P“n”_SE[15:0]

4.12.2 Late Event Counter Registers

Per port (“n”= port number) counters that indicate the number of collision that occurred after the

LateEventThreshold, , which is defined as between 480 and 565 (512 nominal) bit times. Both the Late Event and

collisions will be incremented when this event occurs.

Bit

Bit Name

Access

Bit Description

D15-D0

P“n”_LE[15:0]

R/W

P“n”_LE[15:0]

4.12.3 Collision Counter Registers

Per port (“n”= port number) counters that indicate the number of collisions (COL asserted) .

Bit

Bit Name

Access

Bit Description

D15-D0

P“n”_CO[15:0]

R/W

P“n”_CO[15:0]

4.12.4 Auto-Partition Counter Registers

Per port (“n”= port number) counters that indicate the number of times the port was auto-partitioned.

Bit

Bit Name

Access

Bit Description

D15-D0

P“n”_PART[15:

0]

R/W

P“n”_PART[15:0]

4.12.5 False Carrier Counter Registers

Per port (“n”= port number) counters that indicate the number of times the port was false carrier occurred.

Those counters are valid just for PCS mode port 0 to port 7. As for MII mode , the false carrier counter will be

available on PHY, but some PHY chip manufacturer not support those functions.

Bit

Bit Name

Access

Bit Description

D15-D0

P“n”_FCRS[15:

0]

R/W

P“n”_FCRS[15:0]