L9026 datasheet(11/60 Pages) STMICROELECTRONICS

11 / 60 page

Input / Output

5.1

Parallel inputs (IN0, IN1)

Device has two input pins available. Each input pin is connected by default to one channel (IN0 to channel 2,

IN1 to channel 3). Input Mapping Registers MAP_IN0 and MAP_IN1 can be programmed to connect different

channels to each input pin. The signals driving the channels are an OR combination between PWM_SPI register

status, PWM Generators (according to PWM Generator Output Mapping status), IN0 and IN1 (according to Input

Mapping registers status). See Section 11 SPI for further details.

The logic level of the input pins can be monitored via the status register STA_0. The Input Status Monitor is

operative also when device is in Limp Home mode. If one of the Input pins is set to “high” and the IDLE pin is set

to “low”, the device switches into Limp Home mode and activates the channel mapped by default to the input pins.

5.2

Idle pin (IDLE)

The IDLE pin is used to bring the device into Sleep mode operation when is set to “low” together with IN0, IN1

input pins being at “low” state. When IDLE pin is set to “low” while one of the input pins is set to “high” the device

enters Limp Home mode.

To ensure a proper mode transition, IDLE pin must be set for at least tIDLEFLT_max (transition from “high” to “low”

or from “low” to “high”).

Setting the IDLE pin to “low”, with both IN0 and IN1 also at “low” value, has the following consequences:

•

Device goes in SLEEP MODE

•

All registers in the SPI are reset to default values

•

VDDIO and VBATT Under voltage detection circuits are disabled to decrease current consumption

•

No SPI communication is allowed: SO pin remains in high impedance state also when NCS pin is active.

5.3

Reset pin (NRES, only in VFQFPN32 package option)

The NRES pin, available only for VFQFPN32 version, is the reset input for the device. The function uses the

inverse logic, if the NRES pin is low, the device is held in an internal reset state, all outputs channels are disabled,

and all registers are reset to their default values. An internal pull down will hold the NRES pin asserted in case of

pin open. As default, the state of NRES pin is masked by the logic. The user must send a specific SPI frame to

force the logic to take into account the state of NRES pin.

5.4

Enable (DIS, only in VFQFPN32 package option)

The DIS pin, available only for VFQFPN32 version, is used to enable / disable the output stages. When DIS pin is

high, all channels are disabled if the pin is not masked. An internal pull up will hold the DIS pin asserted in case of

pin open.

When DIS pin is set low, all channels are enabled based on their configuration settings. As default, the DIS pin is

masked by the logic. The user needs to send a specific SPI frame to force the logic to take into account the state

of DIS pin. The status of DIS pin can be monitored reading the STA_0 register.

The DIS pin can be connected to a general purpose output pin of the microcontroller or to an alternative safety

circuit.

5.5

SPI communications (NCS, CLK, SI & SO)

The NCS, CLK, SI & SO pins provide serial communications between the device and the microcontroller. See

Section 11 SPI for details on SPI features, device register functions and electrical characteristics.

L9026

Input / Output

DS13397 - Rev 5

page 11/60

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