MCP48FVB02 datasheet(46/84 Pages) MICROCHIP

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MCP48FVBXX

DS20005466A-page 46

 2015 Microchip Technology Inc.

5.6

Power-Down Operation

To allow the application to conserve power when the

DAC operation is not required, three power-down

modes are available. The Power-Down configuration

bits (PD1:PD0) control the power-down operation

(see Figure 5-10 and Table 5-5). On devices with mul-

tiple DACs, each DACs power-down mode is individu-

ally controllable. All power-down modes do the

following:

• Turn off most of the DAC module’s internal circuits

(output op amp, resistor ladder, et al.)

• Op amp output becomes high-impedance to the

VOUT pin

• Disconnects resistor ladder from reference

voltage (VRL)

Depending on the selected power-down mode, the

following will occur:

•VOUT pin is switched to one of two resistive

pull-downs (see Table 5-5):

-100 k

 (typical)

-1 k

 (typical)

• Op amp is powered-down and the VOUT pin

becomes high-impedance.

There is a delay (TPDE) between the PD1:PD0 bits

changing from ‘00’ to either ‘01’, ‘10’ or ‘11’ with the

op amp no longer driving the VOUT output and the

pull-down resistors sinking current.

In any of the power-down modes where the VOUT pin is

not externally connected (sinking or sourcing current),

the power-down current will typically be ~650 nA for a

single-DAC device. As the number of DACs increases,

the device’s power-down current will also increase.

The Power-Down bits are modified by using a write

command to the volatile Power-Down register, or a POR

event which loads the default Power-Down register

values to the volatile Power-Down register.

Section 7.0, “SPI Commands”

describes the SPI

commands. The Write Command can be used to

update the volatile PD1:PD0 bits.

FIGURE 5-10:

VOUT Power-Down Block

Diagram.

Table 5-6 shows the current sources for the DAC based

on the selected source of the DAC’s reference voltage

and if the device is in normal operating mode or one of

the power-down modes.

Note:

The SPI serial interface circuit is not

affected by the Power-Down mode. This

circuit remains active in order to receive

any command that might come from the

host controller device.

TABLE 5-5:

POWER-DOWN BITS AND

OUTPUT RESISTIVE LOAD

PD1

PD0

Function

Normal operation

 resistor to ground

100 k

 resistor to ground

Open circuit

TABLE 5-6:

DAC CURRENT SOURCES

Device VDD

Current

Source

PD1:0 = ‘00’,

VREF1:0 =

PD1:0

 ‘00’,

VREF1:0 =

Output

Op Amp

Resistor

Ladder

N (1)

N N (1) N

RL Op Amp

Band Gap

Note 1:

Current is sourced from the VREF pin, not

the device VDD.

Gain

VOUT

PD1:PD0

VDD

PD1:PD0

Note 1:

Gain options are 1x and 2x.

(1)

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