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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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MM74HC155N Arkusz danych(PDF) 1 Page - National Semiconductor (TI) |
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MM74HC155N Arkusz danych(HTML) 1 Page - National Semiconductor (TI) |
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1 / 4 page  TLF8364 January 1988 MM54HC155MM74HC155 Dual 2-To-4 Line DecoderDemultiplexers General Description The MM54HC155MM74HC155 is a high speed silicon-gate CMOS decoderdemultiplexer It utilizes advanced silicon- gate CMOS technology and features dual 1-line-to-4-line demultiplexers with independent strobes and common bina- ry-address inputs When both sections are enabled by the strobes the common address inputs sequentially select and route associated input data to the appropriate output of each section The individual strobes permit activating or in- hibiting each of the 4-bit sections as desired Data applied to input C1 is inverted at its outputs and data applied to C2 is non-inverted at its outputs The inverter following the C1 data input permits use as a 3-to-8-line decoder or 1-to-8- line demultiplexer without gating All inputs to the decoder are protected from damage due to electrostatic discharge by diodes to VCC and Ground The device is capable of driving 10 low power Schottky TTL equivalent loads The MM54HC155MM74HC155 is functionally and pin equivalent to the 54LS15574LS155 with the advantage of reduced power consumption Features Y Applications Dual 2-to-4-line decoder Dual 1-to-4-line demultiplexer 3-to-8-line decoder 1-to-8-line demultiplexer Y Typical propagation delay 22 ns Y Low quiescent current 80 mA maximum (74HC series) Y Wide operating range 2V – 6V Connect and Logic Diagram TLF8364 – 1 Order Number MM54HC155 or MM74HC155 Truth Tables 2-to-4-Line Decoder or 1-Line to 4-line Demultiplexer Inputs Outputs Select Strobe Data B A G1 C1 1Y0 1Y1 1Y2 1Y3 X X H X HHHH LL L H L H H H LH L H H L H H HL L H H H L H HH L H H H H L X X X L HHHH Inputs Outputs Select Strobe Data B A G2 C2 2Y0 2Y1 2Y2 2Y3 X X H X HHHH LL L L L H H H LH L L H L H H HL L L H H L H HH L L H H H L X X X H HHHH 3-Line-to-8-Line Decoder or 1-Line-to-8-Line Demultiplexer Inputs Outputs Select Strobe (0) (1) (2) (3) (4) (5) (6) (7) Or Data IC B A IG 2Y0 2Y1 2Y2 2Y3 1Y0 1Y1 1Y2 1Y3 X X X H HHHHHHHH L L L L L H HHHHHH L L H L H L HHHHHH L H L L HH L H HHHH L H H L HHH L H HHH H L L L HHHH L HHH H L H L HHHHH L H H H H L L HHHHHH L H H H H L HHHHHHH L IC e inputs C1 and C2 connected together IG e inputs G1 and G2 connected together H e high level L e low level X e don’t care C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
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