MCP48FVB08 datasheet(75/112 Pages) MICROCHIP

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DS20006362A-page 75

MCP48FXBX4/8

6.0

SPI SERIAL INTERFACE

MODULE

The MCP48FXBX4/8 devices’ SPI serial interface

module supports the SPI serial protocol specification.

The command format and waveforms for the

MCP48FXBX4/8 are defined in Section 7.0 “SPI

Device Commands”.

6.1

Overview

This

section

discusses

some

the

specific

characteristics of the MCP48FXBX4/8’s serial interface

module.

The following sections discuss some of these

device-specific characteristics:

• SPI Serial Interface

• Interface Pins (CS, SCK, SDI, SDO and

LAT/HVC)

• Communication Data Rates

• POR/BOR

6.2

SPI Serial Interface

The MCP48FXBX4/8 devices support the SPI serial

protocol. This SPI operates in Slave mode (does not

generate the serial clock).

The SPI interface uses up to four pins. These are:

•CS – Chip Select

• SCK – Serial Clock

• SDI – Serial Data In (MOSI)

• SDO – Serial Data Out (MISO)

Typical SPI interfaces are shown in Figure 6-1. In the

SPI interface, the master’s output pin is connected to

the slave’s input pin, and the master’s input pin is

connected to the slave’s output pin.

FIGURE 6-1:

Typical SPI Interface Block

Diagram.

The MCP48FXBX4/8 SPI’s module supports two (of

the four) standard SPI modes. These are Mode 0,0

and 1,1. The SPI mode is determined by the state of

the SCK pin (VIH or VIL) when the CS pin transitions

from inactive (VIH) to active (VIL).

An additional HVC pin is available for High-Voltage

Command support. High-Voltage Commands allow the

device to enable and disable nonvolatile Configuration

bits. Without a high voltage present, those bits are

inhibited from being modified.

The HVC pin is high-voltage tolerant. To enter a High-

Voltage Command, the HVC pin must be greater than

the VIHH voltage.

6.2.1

SPI MODES

The SPI module supports two (of the four) standard

SPI modes. These are Mode 0,0 and 1,1. The mode is

determined by the state of the SDI pin on the rising

edge of the first clock bit (of the 8-bit byte).

6.2.1.1

Mode 0,0

In Mode 0,0:

• SCK Idle state = low (VIL)

• Data are clocked in on the SDI pin on the rising

edge of SCK

• Data are clocked out on the SDO pin on the falling

edge of SCK

6.2.1.2

Mode 1,1

In Mode 1,1:

• SCK Idle state = high (VIH)

• Data are clocked in on the SDI pin on the rising

edge of SCK

• Data are clocked out on the SDO pin on the falling

edge of SCK

6.3

Interface Pins (CS, SCK, SDI, SDO

and LAT/HVC)

The operation of the five interface pins and the High-

Voltage Command (HVC) pin is discussed in this

section. The pins are:

• SDI (Serial Data In)

• SDO (Serial Data Out)

• SCK (Serial Clock)

•CS (Chip Select)

•LAT/HVC (High-Voltage Command)

The serial interface works on either 8-bit or 24-bit

boundaries depending on the selected command. The

Chip Select (CS) pin frames the SPI commands.

MCP48FXBXX

Host

Controller

Typical SPI Interface Connections

Other Devices

(Master)

(Slave)

SDI

SDO

SDI

GPIO

SCK

LAT/HVC

GPIO

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