HCS08 datasheet(94/374 Pages) NXP

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Chapter 6 Parallel Input/Output

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

6.5.11

Port F I/O Registers (PTFD and PTFDD)

Port F parallel I/O function is controlled by the registers listed below.

6.5.12

Port F Pin Control Registers (PTFPE, PTFSE, PTFDS)

In addition to the I/O control, port F pins are controlled by the registers listed below.

321

PTFD7

PTFD6

PTFD5

PTFD4

PTFD3

PTFD2

PTFD1

PTFD0

Reset

000

Figure 6-27. Port F Data Register (PTFD)

Table 6-26. PTFD Register Field Descriptions

Field

Description

7:0

PTFD[7:0]

Port F Data Register Bits— For port F pins that are inputs, reads return the logic level on the pin. For port F

pins that are configured as outputs, reads return the last value written to this register.

Writes are latched into all bits of this register. For port F pins that are configured as outputs, the logic level is

driven out the corresponding MCU pin.

Reset forces PTFD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures

all port pins as high-impedance inputs with pullups disabled.

321

PTFDD7

PTFDD6

PTFDD5

PTFDD4

PTFDD3

PTFDD2

PTFDD1

PTFDD0

Reset

000

Figure 6-28. Data Direction for Port F (PTFDD)

Table 6-27. PTFDD Register Field Descriptions

Field

Description

7:0

PTFDD[7:0]

Data Direction for Port F Bits — These read/write bits control the direction of port F pins and what is read for

PTFD reads.

0 Input (output driver disabled) and reads return the pin value.

1 Output driver enabled for port F bit n and PTFD reads return the contents of PTFDn.

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