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M25P128-VMF6TP Arkusz danych(PDF) 30 Page - STMicroelectronics |
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M25P128-VMF6TP Arkusz danych(HTML) 30 Page - STMicroelectronics |
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30 / 41 page ![]() Initial delivery state M25P128 30/41 Rev. 1 Figure 18. Power-up Timing 8 Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). Table 8. Power-Up Timing and VWI Threshold Symbol Parameter Min. Max. Unit tVSL (1) 1. These parameters are characterized only. VCC(min) to S Low 60 µs tPUW (1) Time delay to Write instruction 1 10 ms VWI Write Inhibit Voltage 1.5 2.5 V VCC AI04009C VCC(min) VWI Reset State of the Device Chip Selection Not Allowed Program, Erase and Write Commands are Rejected by the Device tVSL tPUW time Read Access allowed Device fully accessible VCC(max) |
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