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PD70224 Arkusz danych(PDF) 13 Page - Microchip Technology |
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PD70224 Arkusz danych(HTML) 13 Page - Microchip Technology |
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13 / 25 page ![]() 4.2 Thermal Specifications The following table lists the thermal specifications of PD70224. Table 4-2. Thermal Properties Thermal Resistance Min Typ Max Units θJA 31 °C/W θJL 2.5 °C/W θJC 5 °C/W Note: The θJX numbers assume no forced airflow. Junction temperature is calculated using TJ = TA + (PD x θJA). In particular, θJA is a function of the PCB construction. The stated number above is for a four-layer board in accordance with JESD-51 (JEDEC). 4.3 Recommended PCB Layout The following figures show the PD70224 recommended PCB layout for 40-pin QFN 6 mm × 8 mm. The pad for pins 4, 9, 15, 18, 24, 29, 35, and 38 is missing from the layout because it does not exist in package. Figure 4-2. Top-Layer Copper (mm) '°rf 5 l[) c::::::) � (J'I c::::::) \() C\! c::::::) l[) (\J - 0 r---- 0 4,37 r-3,501 oo oo o........___,� 0 0 0 0 CJ CJ 0 0 0 0 CJ 0 0 0 0 ITT 0....--i l[) """" CJ 0 l[) (X) CJ 0- 0 0 0 0 CJ CJ 0 0 0 0 0 �-+---'---------' oo on nn_ --+--------'- 1. oo_:._r r-= --6.40-- PD70224 Package Information © 2020 Microchip Technology Inc. Datasheet DS00003575C-page 13 |
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