Preliminary

PL611-30

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991

www.phaselink.com Rev 03/03/05 Page 5

Figure 1 below describes how to terminate the differential CMOS outputs of PhaseLink’s PL611-30 Programmable QTC clock

for use with PECL or LVDS inputs.

The unique feature of differential CMOS outputs allows great flexibility for board designers. By standardizing on one termination

scheme you can use the PL611-30 for all your LVDS and PECL clock requirements up to 375MHz.

50

Ω line

50

Ω line

R3

R1

R1

R2

R2

R3

CMOS Output

Complementary

CMOS Output

0V

3.3V

1.59V

2.35V

+3.3V

+3.3V

Complementary

Input

Input

Component selection

For LVDS input

R1 = 360

Ω

R2 = 82

Ω

R3 = 130

Ω

For PECL input

R1 = 130

Ω

R2 = 82

Ω

R3 = 130

Ω

Notes:

Place R1 as close to the CMOS outputs as

possible.

Place R2 and R3 as close to the PECL/LVDS

inputs as possible.

PECL

1.10V

1.40V

LVDS

Figure 1

The above layout allows the PL611-30 to drive either a PECL or LVDS input by simply changing the value of R1.