AS3820 datasheet(22/52 Pages) DIALOG

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AS3820

16-Channel White LED Controller for LCD Backlight

Rev. 1.1

Datasheet

www.dialog-semiconductor.com

22 of 52

05-Feb-2019

8.2 PWM Generators

Figure 8.5 : PWM Generators

8.2.1 Clock and Reset

The clock for the built-in PWM generators can be one of the three different sources listed below:

● Internal RC oscillator with 500kHz

● External clock signal. This is usually the HSYNC signal of the TV

● Digital PLL (DPLL) clock derived from VSYNC

8.2.2 Digital PLL

A DPLL can be used to generate the PWM generator counter clock with a frequency that is a multiple of the VSYNC

frequency. The frequency multiplication factor can be controlled to be either “PWMperiod” or “PLLmulti” by control bit

“PLL_per_sel”.

By default “PLL_per_sel”=”0” to control the frequency by “PWMperiod” which also defines the period for the PWM generators.

If necessary, control bit “PLL_per_sel” can be set to control the frequency multiplication by register “PLLmulti” with 16-bit

resolution and independently of PWMperiod.

PLL_per_sel=0 (default):

fDPLLout fVSYNC PWMperiod

PLL_per_sel=1:

fDPLLout fVSYNC PLLmulti

The VSYNC frequency is determined by measuring the VSYNC period with an internal clock. Since the internal clock

and the external VSYNC signal are asynchronous, the result of the measurement will jitter by one internal clock cycle.

Therefore the generated DPLL-frequency jitters by one clock cycle.

AS3820 Arkusz danych(PDF) 22 Page - Dialog Semiconductor