ADPA7006CHIP datasheet(15/24 Pages) AD

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Data Sheet

ADPA7006CHIP

Rev. 0 | Page 15 of 24

THEORY OF OPERATION

The architecture of the ADPA7006CHIP, a medium power

amplifier, is shown in Figure 51. The ADPA7006CHIP uses

two cascaded, four-stage amplifiers operating in quadrature

between six 90° hybrids.

The input signal is divided evenly in two, and then each signal

is divided in two again. Each path is amplified through three

independent gain stages. The amplified signals are then

combined at the output. This balanced amplifier approach

forms an amplifier with a combined gain of 23 dB and a PSAT

value of 28 dBm.

A portion of the RF output signal is directionally coupled to a

diode for detection of the RF output power. When the diode is

dc biased, the diode rectifies the RF power and makes the RF

power available for measurement as a dc voltage at VDET. To

allow temperature compensation of VDET, an identical and

symmetrically located circuit, minus the coupled RF power, is

available via VREF. Taking the difference of VREF − VDET

provides a temperature compensated signal that is proportional

to the RF output (see Figure 51).

VDD1B

VGGB

VDD2B

VDD3B

VDD4B

VDD1A

RFIN

RFOUT

VGGA

VDD2A

VDD3A

VDD4A

Figure 51. ADPA7006CHIP Architecture

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