Preliminary

PLL600-27F

Low Power 5 Output XO 10MHz to 52MHz

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 08/12/04 Page 1

FEATURES

• Generates 5 CMOS outputs.

• Low phase noise (-130 dBc @ 10kHz offset).

• Low jitter (RMS): 2.5ps period jitter.

• 12mA drive capability at TTL output.

• 1.62V to 3.63V DC operation.

• Available in 14 pin 150mil SOIC.

DESCRIPTION

The PLL600-27F is part of PhaseLink’s low cost

family of XO IC’s, designed to replace multiple XO

solutions saving the cost and board space of clock

distribution buffers. In addition, it provides among

the lowest current on the market for the 10MHz to

52MHz range. It accepts input crystals from 10 to

52MHz (fundamental resonant mode) and provides

low phase noise (<-130dBc at 10kHz offset at

30MHz), and very low jitter (2.5 ps RMS period jitter)

outputs.

PIN ASSIGNMENT

1

2

3

4

5

6

7

8

9

10

11

12

13

14

XOUT

GND

CLK5

VDD

CLK4

VDD

CLK3

XIN/FIN

GND

CLK1

GND

CLK2

GND

N/C

BLOCK DIAGRAM

CLK1

CLK2

CLK3

XIN/FIN

XOUT

XTAL

OSC

CLK4

CLK5