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PLL702-05SC-R Arkusz danych(PDF) 4 Page - PhaseLink Corporation |
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PLL702-05SC-R Arkusz danych(HTML) 4 Page - PhaseLink Corporation |
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4 / 6 page ![]() PLL702-05 Low EMI Peripheral Clock Generator for Notebook 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 08/12/04 Page 4 Electrical Specifications 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage VDD 4.6 V Input Voltage, dc VI -0.5 VDD+0.5 V Output Voltage, dc VO -0.5 VDD+0.5 V Storage Temperature TS -65 150 °C Ambient Operating Temperature* TA -40 85 °C Junction Temperature TJ 125 °C Lead Temperature (soldering, 10s) 260 °C ESD Protection, Human Body Model 2 kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. AC Specifications PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS 14.31818 MHz Input Frequency (to be set via XTAL_SEL) +/- 20ppm accuracy 24.576 MHz Output Rise Time 10% to 90% with no load 0.5 ns Output Fall Time 90% to 10% with no load 0.5 ns Duty Cycle At VDD/2 40 50 60 % Max. Absolute Period Jitter Long term, No SST 500 ps Max. Jitter, cycle to cycle Long term + Short term 400 ps Clock Settle Time 22 25 ms Crystal Load Capacitance Excluding PCB parasitics 21 pF Crystal ESR 30 Ω |
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