USB7206CSLASHKDX datasheet(46/56 Pages) MICROCHIP

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2021 Microchip Technology Inc.

DS00003850A-page 46

USB7206C

9.7

Clock Specifications

The device can accept either a 25MHz crystal or a 25MHz single-ended clock oscillator input. If the single-ended clock

oscillator method is implemented,

XTALO should be left unconnected and XTALI/CLK_IN should be driven with a

nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.

It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals

(

XTALI/XTALO). The following circuit design (Figure 9-8) and specifications (Table 9-11) are required to ensure proper

operation.

9.7.1

CRYSTAL SPECIFICATIONS

It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals

(

XTALI/XTALO). Refer to Table 9-11 for the recommended crystal specifications.

FIGURE 9-8:

25MHZ CRYSTAL CIRCUIT

TABLE 9-11: CRYSTAL SPECIFICATIONS

Parameter

Symbol

Min

Nom

Max

Units

Notes

Crystal Cut

AT, typ

Crystal Oscillation Mode

Fundamental Mode

Crystal Calibration Mode

Parallel Resonant Mode

Frequency

Ffund

25.000

MHz

Frequency Tolerance @ 25oC

Ftol

±50

PPM

Frequency Stability Over Temp

Ftemp

±50

PPM

Frequency Deviation Over Time

Fage

±3 to 5

PPM

Note 7

Total Allowable PPM Budget

±100

PPM

Shunt Capacitance

7 typ

Load Capacitance

20 typ

Drive Level

100

Equivalent Series Resistance

Operating Temperature Range

Note 8

Note 9

XTALI/CLK_IN Pin Capacitance

3 typ

Note 10

XTALO Pin Capacitance

3 typ

Note 10

USB7206C

XTALO

XTALI

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