USB7216CSLASHKDX datasheet(12/60 Pages) MICROCHIP

12 / 60 page

USB7216C

DS00003851A-page 12



2021 Microchip Technology Inc.

SPI Data 3-0

SPI_D[3:0]

I/O-U

SPI Data 3-0. If the SPI interface is enabled,

these signals function as Data 3 through 0.

Note 3-1

SPI_D0 operates as the

CFG_BC_EN s trap if

external SPI memory is not

used. It must be terminated

with the selected strap

resistor to 3.3V or GND.

SPI_ D[1 :3] should be

connected to GND through

a weak pull-down.

Note 3-1

SPI Chip

Enable

SPI_CE_N

I/O12

Active low SPI chip enable input. If the SPI

interface is enabled, this pin must be driven

high in powerdown states.

Note 3-2

Operates

the

CFG_NON_REM strap if

external SPI memory is not

used. It must be terminated

with the selected strap

resistor to 3.3V or GND.

Note 3-2

USB Type-C Connector Control

Downstream

Port 1 Type-C

Voltage Monitor

DP1_VBUS_MON

AIO

Used to detect Type-C VBUS vSafe5V and

vSafe0V states on Port 1. A nominal voltage

of 2.7V (2.4V min -3.0V max) is required to

detect the presence of vSafe5V.

Externally, VBUS can be as high as 5.25 V,

which can be damaging to this pin. The

amplitude of VBUS must be reduced by a

voltage divider. The recommended voltage

divider is shown below. 1% tolerance resis-

tors are recommended.

For proper Type-C port operation, it is criti-

cal that this pin actually be connected to

VBUS of the port through the recommended

resistor divider. This pin should not be tied

permanently to a fixed voltage power rail.

Note 3-3

If unused: Weak pull-down

to GND. This pin may be

left unused if Port 1 is

disabled or reconfigured to

operate in legacy Type-A

mod e

thro ug h

hu b

configuration.

Note 3-3

TABLE 3-1:

PIN DESCRIPTIONS (CONTINUED)

Name

Symbol

Buffer

Type

Description

If Unused

VBUS_P1

43K

DP1_VBUS_MON

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