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ICS671M-06ILF Arkusz danych(PDF) 1 Page - Integrated Circuit Systems |
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ICS671M-06ILF Arkusz danych(HTML) 1 Page - Integrated Circuit Systems |
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1 / 6 page ![]() ICS671-06 MDS 671-06 D 1 Revision 050405 Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER Description The ICS671-06 is a low phase noise, high-speed PLL-based, 8 output, low skew zero delay buffer. Based on ICS’ proprietary low jitter Phase-Locked Loop (PLL) techniques, the device provides eight low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero delay), or directly from the input (for testing), and can be set to tri-state mode or to stop at a low level. For normal operation as a zero delay buffer, any output clock is tied to the FBIN pin. ICS manufactures the largest variety of clock generators and buffers and is the largest clock supplier in the world. Features • Clock outputs from 10 to 133 MHz • Zero input-output delay • Eight low skew (<200 ps) outputs • Device-to-device skew <700 ps • Low jitter (<200 ps) • Full CMOS outputs with 25 mA output drive capability at TTL levels • 5 V tolerant FBIN and CLKIN pins • Tri-state mode for board-level testing • Advanced, low power, sub-micron CMOS process • Operating voltage of 3.3 V • Industrial temperature range available • Packaged in 16-pin SOIC • Available in Pb (lead) free package Not recommended for new designs. See the MK2308-1H for new designs. Block Diagram CLKA4 CLKB1 CLKA3 CLKB2 CLKB3 CLKA2 CLKA1 CLKB4 CLKIN Control Logic 1 0 S2, S1 2 Clock Synthesis PLL FBIN Feedback is shown from CLKB4 for illustration, but may come from any output. VDD 2 GND 2 |
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