2

ICSSSTV16857C

0002F—10/25/02

General Description

Pin Configuration

R

E

B

M

U

N

N

I

PE

M

A

N

N

I

PE

P

Y

TN

O

I

T

P

I

R

C

S

E

D

,

8

1

,

9

1

,

0

2

,

3

2

,

4

2

,

7

,

0

1

,

1

1

,

4

1

,

5

1

1

,

2

,

5

,

6

)

1

:

4

1

(

QT

U

P

T

U

Ot

u

p

t

u

o

a

t

a

D

,

2

2

,

3

1

,

8

,

3

6

4

,

6

3

,

7

2

D

N

GR

W

Pd

n

u

o

r

G

1

2

,

6

1

,

2

1

,

9

,

4Q

D

D

VR

W

Pe

g

a

t

l

o

v

y

l

p

p

u

s

t

u

p

t

u

O

,

1

3

,

0

3

,

9

2

,

6

2

,

5

2

,

2

4

,

1

4

,

0

4

,

3

3

,

2

3

8

4

,

7

4

,

4

4

,

3

4

)

1

:

4

1

(

DT

U

P

N

It

u

p

n

i

a

t

a

D

8

3K

L

CT

U

P

N

It

u

p

n

i

k

c

o

l

c

e

v

i

t

i

s

o

P

9

3#

K

L

CT

U

P

N

It

u

p

n

i

k

c

o

l

c

e

v

i

t

a

g

e

N

5

4

,

7

3

,

8

2D

D

VR

W

Pe

g

a

t

l

o

v

y

l

p

p

u

s

e

r

o

C

4

3#

T

E

S

E

RT

U

P

N

I)

w

o

l

e

v

i

t

c

a

(

t

e

s

e

R

5

3F

E

R

VT

U

P

N

Ie

g

a

t

l

o

v

e

c

n

e

r

e

f

e

r

t

u

p

n

I

except for the LVCMOS RESET# input.

Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive edge

of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#, an

LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTV16857C supports low-power

standby operation. A logic level “Low” at RESET# assures that all internal registers and outputs (Q) are reset to the logic

“Low” state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off. Please note that RESET# must always

be supported with LVCMOS levels at a valid logic state because VREF may not be stable during power-up.

To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held at a logic

“Low” level during power up.

In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#.

Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state,

the register will be cleared and the outputs will be driven to a logic “Low” level quickly relative to the time to disable the

differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power

standby state, the register will become active quickly relative to the time to enable the differential input receivers. When

the data inputs are at a logic level “Low” and the clock is stable during the “Low”-to-”High” transition of RESET# until the

input receivers are fully enabled, the design ensures that the outputs will remain at a logic “Low” level.