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ICS421004AI01 Arkusz danych(PDF) 10 Page - Integrated Circuit Systems |
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ICS421004AI01 Arkusz danych(HTML) 10 Page - Integrated Circuit Systems |
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10 / 13 page ![]() 8421004AGI-01 www.icst.com/products/hiperclocks.html REV. A MACH 29, 2005 10 Integrated Circuit Systems, Inc. ICS8421004I-01 FEMTOCLOCKS™CRYSTAL-TO- HSTL FREQUENCY SYNTHESIZER PRELIMINARY 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 3. To calculate worst case power dissipation into the load, use the following equations which assume a 50 Ω load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (V OH_MIN /R L ) * (V DD_MAX - V OH_MIN ) Pd_L = (V OL_MAX /R L ) * (V DD_MAX - V OL_MAX ) Pd_H = (1V/50 Ω) * (2V - 1V) = 20mW Pd_L = (0.4V/50 Ω) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW FIGURE 3. HSTL DRIVER CIRCUIT AND TERMINATION V DDO V OUT RL 50 Ω Q1 |
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