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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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HCS08 Arkusz danych(PDF) 265 Page - NXP Semiconductors |
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HCS08 Arkusz danych(HTML) 265 Page - NXP Semiconductors |
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265 / 316 page  MC9S08SG8 MCU Series Data Sheet, Rev. 8 Freescale Semiconductor 265 Figure 17-2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during host-to-target transmissions to speed up rising edges. Because the target does not drive the BKGD pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal during this period. Figure 17-2. BDC Host-to-Target Serial Bit Timing EARLIEST START TARGET SENSES BIT LEVEL 10 CYCLES SYNCHRONIZATION UNCERTAINTY BDC CLOCK (TARGET MCU) HOST TRANSMIT 1 HOST TRANSMIT 0 PERCEIVED START OF BIT TIME OF NEXT BIT |
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