HCS08 datasheet(96/316 Pages) NXP

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Chapter 7 Central Processor Unit (S08CPUV2)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

7.3.6.1

Indexed, No Offset (IX)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of

the operand needed to complete the instruction.

7.3.6.2

Indexed, No Offset with Post Increment (IX+)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of

the operand needed to complete the instruction. The index register pair is then incremented

(H:X = H:X + 0x0001) after the operand has been fetched. This addressing mode is only used for MOV

and CBEQ instructions.

7.3.6.3

Indexed, 8-Bit Offset (IX1)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned

8-bit offset included in the instruction as the address of the operand needed to complete the instruction.

7.3.6.4

Indexed, 8-Bit Offset with Post Increment (IX1+)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned

8-bit offset included in the instruction as the address of the operand needed to complete the instruction.

The index register pair is then incremented (H:X = H:X + 0x0001) after the operand has been fetched. This

addressing mode is used only for the CBEQ instruction.

7.3.6.5

Indexed, 16-Bit Offset (IX2)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus a 16-bit offset

included in the instruction as the address of the operand needed to complete the instruction.

7.3.6.6

SP-Relative, 8-Bit Offset (SP1)

This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit

offset included in the instruction as the address of the operand needed to complete the instruction.

7.3.6.7

SP-Relative, 16-Bit Offset (SP2)

This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset

included in the instruction as the address of the operand needed to complete the instruction.

7.4

Special Operations

The CPU performs a few special operations that are similar to instructions but do not have opcodes like

other CPU instructions. In addition, a few instructions such as STOP and WAIT directly affect other MCU

circuitry. This section provides additional information about these operations.

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