DS31256_V01 datasheet(88/183 Pages) MAXIM

88 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

88 of 183

Figure 9-1. Receive DMA Operation

Free Data Buffer Address

00h

08h

10h

Free Queue Descriptors

(circular queue)

00h

04h

08h

Done Queue Descriptors

(circular queue)

Open Descriptor Space

Available for Use by the DMA

Data Buffer Address

Unused

Timestamp

CH #2

Status

0Ch

Free Data Buffer

(up to 8188 bytes)

Free Data Buffer

(up to 8188 bytes)

First Filled

Data Buffer

for Channel 2

Free Packet Descriptors & Data Buffers

Used Packet Descriptors & Data Buffers

Single Filled

Data Buffer

for Channel 5

Second Filled

Data Buffer

for Channel 2

Last Filled

Data Buffer

for Channel 2

Single Filled

Data Buffer

for Channel 9

dmarbd

unused

Free Desc. Ptr.

unused

Free Data Buffer Address

Open Descriptor Space

Available for Use by the DMA

# Bytes Next Desc. Ptr.

Data Buffer Address

Timestamp

CH #5

Status # Bytes Next Desc. Ptr.

Data Buffer Address

Timestamp

CH #2

Status # Bytes Next Desc. Ptr.

Data Buffer Address

Timestamp

CH #2

Status # Bytes Next Desc. Ptr.

Data Buffer Address

Timestamp

CH #9

Status # Bytes Next Desc. Ptr.

EOF Status

CH #5

Desc. Ptr.

EOF Status

CH #2

Desc. Ptr.

EOF Status

CH #9

Desc. Ptr.

EOF Status

CH #

Desc. Ptr.

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