isolated applications,because the internal error amplifier is used to close the regulation loop, the output reaches the

regulation level when SS reaches 1.2 V.

An additional internal offset is added to the FB to ensure that COMP does not reach its upper limit because of

amplifier input offset. This offset is removed (slowly to avoid overshoot) when the SS ramp is complete.

Low Power mode is not supported during SS ramp as it is not necessary.

6.11

Current Limit and Short Circuit Protection

The DC-DC converter is a peak current mode controller; an internal current sense amplifier with a gain of 5 monitors

the voltage across an external current sense resistor and regulates the output based on the current through the

resistor. If the output of the internal current sense amplifier reaches 1.2 V, the converter will truncated the PWM

output, and thus limit the output current.

If the output of the internal current sense amplifier reaches 1.8 V, the controller enters hiccup mode by discharging

the SS capacitor with a constant current that equals 10% of the charging current during ramp up.

This discharge continues until VSS = 50 mV where an internal ~50 Ω MOSFET connected to SS turns on for 25 clock

cycles to ensure the SS capacitor fully discharges to GND before ramping back up and restart. The converter will exit

the hiccup mode when the over current condition is removed.

6.12

Low Power Mode Operation

The devices offer a pulse skipping operation for light load condition, referred to as Low Power Mode (LPM), to

improve the efficiency of light load operation by reducing the power dissipation especially in high frequency switching.

Using an external resistor from RCLP pin to GND, the user can program the output power when the unit enters pulse

skipping.

Pulse skipping mode is disabled until SS ramp is completed, regardless of the LPM status.

6.13

Input (VPP and VCC) Under Voltage Lock Out

The PD interface circuit offers an internal PGOOD signal that can be used to start the DC-DC converter; however, the

threshold of the PGOOD is fixed at VPN_OUT-VPN_IN ≤ 0.7 V. This may not fit all possible applications. Therefore,

the device offers an option to have a programmable UVLO which is tied to level of VPP-VPN_OUT, plus a

programmable hysteresis. The voltage developed across a simple resistor divider is sensed at VINS, and will enable/

disable the PWM controller at a nominal 1.2 V threshold. A third resistor connected between VINS and HYST pins

allows programmable hysteresis. This feature enables the end user to tailor to any desired systems application’s

requirement for turn on and turn off time. In addition to the VPP sensing for UVLO, the devices also have VCC UVLO

to ensure that the PWM controller is always properly powered during operation. These features provide robust

solutions under various systems disturbances.

6.14

External Enable

The PD interface circuit provides an internal PGOOD signal that is used to enable the DC-DC converter when

powered by the PoE input; however, for applications that require input power from a wall adaptor, the internal

PGOOD signal is not functional. For these applications an external enable input is provided, allowing a non-PoE

power source (such as a wall adaptor) the ability to start the DC-DC converter. The Enable pin is active high, and is

driven by a 5 V maximum signal referenced to GND. When the DC-DC converter is powered by the PD interface

(PoE power), the Enable pin will not disable the controller. It may be tied to ground or left floating when not used.

PD70101 and PD70201

Theory of Operation

Datasheet

DS00003738A-page 24