Zakładka z wyszukiwarką danych komponentów
  Polish  ▼
ALLDATASHEET.PL

X  

74ABT373CFCQB Arkusz danych(PDF) 2 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Numer części 74ABT373CFCQB
Szczegółowy opis  Octal Transparent Latch with TRI-STATE Outputs
PDF  16 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Producent  NSC [National Semiconductor (TI)]
Strona internetowa  http://www.national.com
Logo NSC - National Semiconductor (TI)

74ABT373CFCQB Arkusz danych(HTML) 2 Page - National Semiconductor (TI)

  74ABT373CFCQB Datasheet HTML 1Page - National Semiconductor (TI) 74ABT373CFCQB Datasheet HTML 2Page - National Semiconductor (TI) 74ABT373CFCQB Datasheet HTML 3Page - National Semiconductor (TI) 74ABT373CFCQB Datasheet HTML 4Page - National Semiconductor (TI) 74ABT373CFCQB Datasheet HTML 5Page - National Semiconductor (TI) 74ABT373CFCQB Datasheet HTML 6Page - National Semiconductor (TI) 74ABT373CFCQB Datasheet HTML 7Page - National Semiconductor (TI) 74ABT373CFCQB Datasheet HTML 8Page - National Semiconductor (TI) 74ABT373CFCQB Datasheet HTML 9Page - National Semiconductor (TI) Next Button
Zoom Inzoom in Zoom Outzoom out
 2 / 16 page
background image
Functional Description
The
’ABT373
contains
eight
D-type
latches
with
TRI-STATE output buffers When the Latch Enable (LE) in-
put is HIGH data on the Dn inputs enters the latches In this
condition the latches are transparent ie a latch output will
change state each time its D input changes When LE is
LOW the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
sition of LE The TRI-STATE buffers are controlled by the
Output Enable (OE) input When OE is LOW the buffers are
in the bi-state mode When OE is HIGH the buffers are in
the high impedance mode but this does not interfere with
entering new data into the latches
Truth Table
Inputs
Output
LE
OE
Dn
On
HL
H
H
HL
L
L
LL
X
On (no change)
XH
X
Z
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Z e High Impedance State
Logic Diagram
TLF11547 – 3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16


Arkusz danych Pobierz

Go To PDF Page


Link URL



Czy Alldatasheet okazała się pomocna?  [ DONATE ] 

O Alldatasheet   |   Reklama   |   Kontakt   |   Polityka prywatności   |   Link do karty katalogowej    |   Linki   |   Lista producentów
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com