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AS5050A Arkusz danych(PDF) 12 Page - ams AG |
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AS5050A Arkusz danych(HTML) 12 Page - ams AG |
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12 / 31 page ![]() Page 12 ams Datasheet Document Feedback [v2-06] 2014-Oct-14 AS5050A − SPI Inter face The 16-bit SPI interface provides read/write access to the on-chip registers. The interface only supports slave operation mode. It communicates at clock rates up to 10 MHz. The AS5050A SPI uses mode=1 (CPOL=0, CPHA=1) to exchange data. As shown in Figure 12, a data transfer starts with the falling edge of CSn (SCL is low). The AS5050A samples the MOSI input on the falling edge of SCL. SPI commands are executed at the end of the frame (rising edge of CSn). The bit order is MSB first. Data is protected by parity. SPI Timing Figure 12: SPI Timing Diagram SPI Interface CSn (Input) CLK (Input) MOSI (Input) MISO (Output) tclk tL tMOSI tMISO tOZ tOZ tH tCSn tclkL tclkH data[15] data[15] data[14] data[14] data[0] data[0] |
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