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SMD-00191 Rev D

Subject to Change Without Notice

PFD1K

Overview:

The functional block diagram for the PFD1K is shown above. It contains two parallel programmable

prescalers which frequency divide the reference and VCO inputs to the phase frequency detector.

Reference input divide ratio R is determined as follows:

R = R6 * 26 + R5 * 25 + R4 * 24 + R3 * 23 + R2 * 22 + R1 * 21 + R0 * 20

where R6 thru R0 have values of 0 or 1. (All bits set to 0 results in a divide ratio of 1). Similarly, the

divide ratio for the VCO input is set by V6 thru V0.

The core phase frequency detector can be operated up to a reference frequency of 8 GHz. The out-

put of the phase frequency detector drives two programmable charge pumps. The amplitudes of the

UP and Down pulses from the charge pumps can be controlled digitally by setting A[3:0]. There is

also an analog adjustment at the VADJ* pin.

The divided reference and VCO signals may be monitored at the DRO and DVO outputs respective-

ly. Analog adjustments, VADV* and VADR* can be used to control the amplitudes of DVO and DRO,

or to disable DVO and DRO in order to reduce power consumption. With the exception of DRO and

DVO, all of the RF inputs and outputs of the PFD1K are fully differential CML compatible levels so

that they are easy to interface with other logic.

* VADJ, VADV and VADR are not shown in the block diagram.

Theory of Operation

Functional Block Diagram