Zakładka z wyszukiwarką danych komponentów
  Polish  ▼
ALLDATASHEET.PL

X  

SY75604B Arkusz danych(PDF) 10 Page - Microchip Technology

Numer części SY75604B
Szczegółowy opis  2/4 Outputs Ultra-Low Additive Jitter PCIe 1/2/3/4/5 Clock Buffer
PDF  26 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Producent  MICROCHIP [Microchip Technology]
Strona internetowa  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

SY75604B Arkusz danych(HTML) 10 Page - Microchip Technology

Back Button SY75604B Datasheet HTML 6Page - Microchip Technology SY75604B Datasheet HTML 7Page - Microchip Technology SY75604B Datasheet HTML 8Page - Microchip Technology SY75604B Datasheet HTML 9Page - Microchip Technology SY75604B Datasheet HTML 10Page - Microchip Technology SY75604B Datasheet HTML 11Page - Microchip Technology SY75604B Datasheet HTML 12Page - Microchip Technology SY75604B Datasheet HTML 13Page - Microchip Technology SY75604B Datasheet HTML 14Page - Microchip Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 26 page
background image
SY75602A/02B/603A/03B/604A/04B
DS20006508B-page 10
2021 Microchip Technology Inc. and its subsidiaries
3.0
PIN DESCRIPTIONS
All device inputs and outputs are LP-HCSL unless described otherwise. The Type column uses the following symbols:
• I: Input
• IPD: Input with 100 kΩ internal pull-down resistor
• O: Output
• P: Power supply
The descriptions of the pins are listed in Table 3-1 and Table 3-2.
TABLE 3-1:
SY75602A/02B PIN FUNCTION TABLE
Pin Number Pin Name
Type
Description
Input Reference
1
IN_p
I
Differential/Single Ended Input Reference
Input frequency range >0 Hz to 250 MHz.
Note 1: >0 Hz means frequency higher than DC. On the power up, the
device needs four clock cycles before the outputs get enabled. This feature
filters any initial glitch or runt pulse from the clock source.
Note 2: The differential input has hysteresis of 30 mV that prevents outputs
from randomly toggling when both p and n inputs are at the same voltage
level. For example, when p and n inputs are held low as in the case when
the buffer is driven from an HCSL driver that is disabled.
2
IN_n
Output Clocks
3
OUT0_p
O
Ultra-Low Additive Jitter Differential Outputs 0 and 1
Output frequency range >0 Hz to 250 MHz.
4
OUT0_n
6
OUT1_p
7
OUT1_n
Power and Ground
8
VDD
P
Positive Supply Voltage: Connect to either 3.3V, 2.5V, or 1.8V supply.
5
GND
P
Ground: Connect to ground.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26


Arkusz danych Pobierz

Go To PDF Page


Link URL



Czy Alldatasheet okazała się pomocna?  [ DONATE ] 

O Alldatasheet   |   Reklama   |   Kontakt   |   Polityka prywatności   |   Link do karty katalogowej    |   Linki   |   Lista producentów
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com