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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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STM32F469AE Arkusz danych(PDF) 34 Page - STMicroelectronics |
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STM32F469AE Arkusz danych(HTML) 34 Page - STMicroelectronics |
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34 / 220 page  Functional overview STM32F469xx 34/220 DS11189 Rev 7 The following conditions must be respected: VDD must always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for VDD to reach 1.7 V, then PA0 must be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 11). Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower than the time for VDD to reach 1.7 V, then PA0 can be asserted low externally (see Figure 12). If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a reset must be asserted on PA0 pin. Note: The minimum value of V12 depends on the maximum frequency targeted in the application (see Operating conditions). Figure 11. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1 , VCAP_2 stabilization 1. This figure is valid whatever the internal reset mode (ON or OFF). ai18491g VDD time Min V12 PDR = 1.7 or 1.8 V VCAP_1, VCAP_2 V12 NRST time PA0 |
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