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STM32F730Z8 Arkusz danych(PDF) 46 Page - STMicroelectronics |
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STM32F730Z8 Arkusz danych(HTML) 46 Page - STMicroelectronics |
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46 / 202 page  Functional overview STM32F730x8 46/202 DS12536 Rev 2 • Internal FS OTG PHY support • For the STM32F730x8 devices: External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. • For the STM32F730x8 devices: Internal HS OTG PHY support. • Internal USB DMA • HNP/SNP/IP inside (no need for any external resistor) • For OTG/Host modes, a power switch is needed in case bus-powered devices are connected Universal Serial Bus controller on-the-go High-Speed PHY controller (USBPHYC) only on STM32F730x8 devices. The USB HS PHY controller: – Sets the PHYPLL1/2 values for the PHY HS – Sets the other controls on the PHY HS – Controls and monitors the USB PHY’s LDO 3.31 Random number generator (RNG) All the devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 3.32 Advanced encryption standard hardware accelerator (AES) The devices embed an AES hardware accelerator which can be used to both encipher and decipher data using AES algorithm. |
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