ADE1202 datasheet(23/42 Pages) AD

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Data Sheet

ADE1202

Rev. 0 | Page 23 of 42

GATE DRIVE

The GATE pin is used to drive two external high voltage

enhancement mode FETs, Q1 and Q2. After power-up, the

GATE pin is biased at VGATENOM to allow Q1 and Q2 to conduct

the constant current while protecting the LOADx pins, as

shown in Figure 37. Two 10 Ω, external, gate current limiting

resistors (R13 and R14), and a 0.1 µF gate capacitor (C5) are

required for stability. Table 1 shows the nominal VGATENOM

voltage (see Figure 37).

During a pulsed current, VGATENOM is regulated to reduce the

voltage on the LOADx pins to minimize on-chip power

consumption.

When two FETs are conducting, the corresponding LOADx pin

for the FET with the larger gate source voltage (VGS) is at 0.6 V

and the other LOADx pin is at a higher voltage, as determined

by FET mismatch.

When one FET is conducting, the corresponding LOADx pin is

at 2.8 V, or as close as possible based on FET VGS. The LOADx pin

voltage is higher with one FET conducting to allow a fast

response in case the other FET must turn on.

After a pulsed current period, the GATE voltage is regulated

back to VGATENOM. The ADE1202 is compatible with FETs with a

maximum VGS of 6 V. It is recommended to use the same FET

for both channels, and FET to FET mismatch of up to 2 V is

supported.

GATE

IN2

IN1

R13

LOAD1

R14

10Ω

LOAD2

0.1µF

MOV

275VAC/350VDC

≤300V

10nF

ADE1202

GNDF

MOV

275VAC/350VDC

10Ω

R10

10Ω

10nF

VGS2

VGS1

R12

1.1kΩ

R11

1.1kΩ

1nF

≤300V

95.3kΩ

Figure 37. FET Gate Control

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